30 Apr
2013
30 Apr
'13
3:41 p.m.
On 29/04/13 21:11, David Riley wrote:
On Apr 29, 2013, at 3:56 PM, Rob Doyle <radioengr
at gmail.com> wrote:
The speed of the /30 is so
much lower than the capability of the FPGA
(1.5MHz vs 50MHz) that it wasn't really an issue. However, I have gone
On 4/29/2013 8:59 AM, David Riley wrote:
I think the 360/30 FPGA
(http://www.ljw.me.uk/ibm360/vhdl/) does the
same. To be clear, it's DOABLE on an FPGA, but the timing analyzers
don't like it very much. Add to that the fact that the built-in
flip flops are strictly edge triggered in most technologies and you
have a hard time doing something as simple as an RS latch (some of
the true CPLDs around, like Xilinx's CoolRunner line, still have
true RS options available, but they're very small). Clockless logic is something that comes up now
and then in ASIC
and FPGA circles, but it never seems to pan out (I remember Sun
doing something with it about a decade ago as well). I don't
know if it's because the tools are too hard to design or what,
but there must be some reason it never comes to anything (or at
least hasn't since the late '60s).
There is an IBM1130 CPU that is accurately implemented using
asynchronous logic in a standard FPGA.
See: http://ibm1130.blogspot.com/
This technique is probably not for the timid. from asynchronous S/R FFs and transparent latches to
synchronous
(edge-triggered) versions running from the global 50MHz clock (so
effectively the same thing, but with a 0-20ns delay). I think this has
got rid of a some inconsistent behaviour, possibly caused by routing
delays which change from build to build.
In general, if you're looking to implement something that was
originally designed around asynchronous logic in a modern FPGA,
you're generally better off trying to figure out how to make it run
with synchronous logic instead of implementing it 100% faithfully to
the schematic. A lot of the time, it's actually not particularly
hard to do; for example, microprocessor RD and WR lines often
implicitly act as clocks, which you can use to your advantage when
coding bus interfaces that use them.
- Dave
I didn't want to get into redesigning things to work synchronously, but
if I wanted to crank the speed up then I would have to. Luckily there
is no reason to make it run faster!
For anyone that's interested in a progress report, I'm currently working
on a SD card interface to emulate the 2311 (7MB) drives, using Hercules
CKD files. So far the SD/SDHC interface is working, and it can mount
the FAT16/32 filesystem, find the CKD files in the root directory, and
read the first cluster. Next step is the cluster chaining and CKD file
parsing. Everything is in VHDL inside the same Spartan3 FPGA as the CPU.
--
Lawrence Wilkinson lawrence at ljw.me.uk
The IBM 360/30 page http://www.ljw.me.uk/ibm360