68K ISA project

On Tue, Jul 13, 2010 at 2:41 PM, Henk Gooijen <henk.gooijen at hotmail.com> wrote: Sorry... HTML, not PDFs, but still easy to read. I've read most of them through that archive. I might even have one or two in a folder of ancient docs, but I doubt it's one of the last 4 issues (the ones that _aren't_ available to read). Quite. I learned assembler as first language on I don't recall seeing anything in a DIP package badged faster than 12.5MHz, but perhaps one of the newer dies (68EC000?) might go faster and still be bus and register-compatible with the original? I'm sure there'd be some interest but based on my experience, you should probably set performance expectations around a nominal 8MHz CPU (since they are so much more common than the faster varieties). If you make a "DTACK Grounded" 68000 SBC design, modern SRAM and EPROM are plenty fast enough to keep up and it _would_ keep the design simple (two 8-bit-wide ROMs, two 8-bit-wide SRAMs, whatever I/O, which might be your only bottleneck, depending on what serial chip you might pick - we had to do software throttling on our old 4MHz Z8530 serial design - lots of careful coding and uncareful sprinkling of NOPs to dodge back-to-back reads and writes of the SIO). It really needn't be much more complex than a 6809 design with a 16-bit bus. Something that might be an interesting alternative to a VT220 might be an HD44780-type textual LCD, especially a wide format panel like 2x40 (or the less common but impressive 4x40). OTOH, depending on your ASCII art, it wouldn't be difficult to rig up an AVR microcontroller to interpret your selected terminal codes and drive the LCD panel as an option. I'm always interested in discussing 68000 designs real and imagined. I first ran across a preliminary spec sheet back when I was using a PET every week and five years later was using them every day at work. Cheers, -ethan