FPGAs and PDP-11's

please see comments embedded below. Dick -----Original Message----- From: Pete Turnbull <pete(a)dunnington.u-net.com> To: Discussion re-collecting of classic computers <classiccmp(a)u.washington.edu> Date: Friday, August 27, 1999 4:41 PM Subject: Re: FPGAs and PDP-11's This is a case like the TXA, etc, which is a simple transfer from one register to another with no ALU operation. Well, on each cycle it flows the PCL through the ALU, adding zero with carry. The indexing operations and stack pointer op's also do arithmetic on the ABL and SP. Likewise, the INC and DEC instructions flow data from the register block to the register block through the ALU. Still, there are no register operations which require access to more than one register's contents at a time. The critical issue being that the registers can simply be implemented in a RAM. In fact, it appears that the RAM block might best be implemented in an inverting RAM like the 74189 (actually a 16x4, but two would work) because the arithmetic unit might work quite well as a simple adder/subtractor, with a multiplexer as the shifter unit. The fact that this RAM has separate inputs and outputs makes the TTL model very simple. The indexing operations involve arithmetic on memory address operands rather than on register contents. The instruction contains the absolute address or a pointer to it, and an index register contains an offset. Arithmetic is done on the address components and only on one element in the register set. Either one or two address bytes are part of the instruction, depending on the mode, and the index register contains the offset to be added to the low address byte either from the instruction or from the table to which a zero page pointer directs it and 16-bit arithmetic is done on that using only one byte from the register set. These indexed instructions using indirection take as many as 6 (7 if a page boundary is crossed) cycles. The arithmetic can always be done using the ALU, however.