Fwd: Naked Mini Broke

Iggy Drougge wrote: [snip] Particularly in space-based applications, where flight qualification for man-rated hardware is a pangalactic bitch. I'm sure that's a component -- even contemporary dynamic memory is less rad hard than you'd probably like, but that's hardly the overriding reason. My increasingly dim memory suggests that the processor are slightly modified 1750A machines. There was some indication that they were a derivative of the processor using in the F-16, but I never was able to verify that. Being '70s designs suggests that core would have been the only real option. I have no idea if the processors are being swapped out as part of the flight deck modernization program. If so it can't be too radical a departure from the existing architecture, since only one orbiter has completed that modification cycle and the thought of having two sets of tools for building the code loads for the orbiters staggers the mind. Oh yeah, that's the other thing. The code load for each orbiter is unique to the mission, and there's no real executive function -- it's a bunch of cooperating real-time tasks, such that if one pukes out it probably takes out the rest. There's been at least one documented case where the flight code load, during on-the-pad prelaunch simulation, dropped the ball and the flight deck displays ended up with the shuttle's answer to the BSOD -- an 'X' drawn through the flight deck displays. If you think that's odd, you should check out the way that voting works... -- Chris Kennedy chris(a)mainecoon.com http://www.mainecoon.com PGP fingerprint: 4E99 10B6 7253 B048 6685 6CBC 55E1 20A3 108D AB97