28 Aug
2020
28 Aug
'20
1:40 p.m.
On Aug 28, 2020, at 3:31 PM, Warner Losh via cctalk
<cctalk at classiccmp.org> wrote:
It's been over a decade, but I'm pretty sure that 1 lane to 4 lane mode is just a
width change. But when we started using 50 MHz capable cards and wanted to support those,
I learned about that clock edge changeover. Both are 4 lanes wide, and the fast devices
also support the slower clock and I believe initially come up in that mode. So you end up
issuing a "go fast" command and as part of that you have to tell the FPGA to
switch its latches to the other mode, and you do this dance carefully so you don't see
any false error indications due to the latching mode change.
paul
On 8/28/20 1:10 PM, Paul Koning wrote:
...
One oddity I remember from a decade ago is that it has a high speed mode
where the clock speed is doubled. That's not strange. What's strange is
that when you do this, the device switches from clocking data on the rising
edge to clocking on the falling edge, or the other way around, I don't
remember which. Fortunately I wasn't the hardware designer who had to cope
with all that strangeness.
I thought it was going from SPI mode to MMC mode that did this, not the
double clocking nor the 1bit to 4bit bus steps.