KA630 guru?

If only you'd bought either of the VMS Internals books I've just auctioned on epay :-) The way VAX/VMS turns on memory management is as follows. (Yours looks like it's something else, some console test code, but the same principles should apply). The code sets up a mapping such that a physical address N, a system virtual address and a P0 address N (using a part of the SPT that is also a P0 page table). So the sequence goes: [PHYSICAL] something irrelevant [PHYSICAL] MTPR #1, 38 [P0] JMP @#10$ [SYSTEM] 10$: next-instruction Now your numbers are going to be different but in principle the code must do the same thing. Your MTPR executes in physical address mode (mapen off) at address 0x0219. The next instruction will be 0x21c, but by them mapping will be on, so this must be a virtual address and it will always be a P0 address (since the preceding physical address must be less than the 4GB maximum that the VAX architecture allows). I assume that your "v" command is dumping your idea of the system and process page tables. Are you sure that you've correctly emulated the various registers involved? The text says that if the code you jump to lives in PFN n, then the mapping sets up P0LR with n+2 and P0BR with the SVA that is n longwords smaller than the SPTE that maps this code. So my guess is that you've failed somewhere to accept an attempt to set up the page tables as expected. I'd work back through the code and see where it sets those up (this may be non-trivial) and then verify that you emulate that stuff properly. Admittedly I'm assuming that whoever coded up this test in the KA630 console ROM used the same mapping technique as VAX/VMS, but I would have thought it a safe assumption that insufficient mind-altering drugs exist in the Universe for someone to sit down and work out an alternative methode that looks like the original but is different :-) Antonio -- --------------- Antonio Carlini arcarlini(a)iee.org