15 Dec
2008
15 Dec
'08
6:03 p.m.
Rich Alderson wrote:
[snip]
I would consider the Sigma 5/6/7/9 series RISC for the day. Basic
load/store, multiple register sets. It
did have a few string instructions (move byte string, compare byte
string,edit byte string) but in general load/store.
Since the design was async most instructions completed in 1 clock
"cycle". The 5/6/7/9 were 32 bit.
The 16 bit Sigma 2/3 series had a nice small instruction set that I once
considered implementing in a
CPLD or FPGA. Just never had the time.
*IBM system 360/370/... [Multi-GP-register -
store organisation with a
sprinkling of store-store operarions]
*DEC VAX (and its simpler predecessor, the PDP-11) [address-modes-R-us]
The RISC before there ws RISC:
*CDC6600
The PDP-10 is often described this way.
The classic 36-bit architectures
*IBM709/7090/7094 [single accumulator/few index
registers]
*GE6xx/Multics/Honeywell L66 [similar architecture, taken to its limits, and
(in later models) even more address modes than a VAX]
...and I'm surprised that you don't consider the PDP-10 to be a classic 36-bit
architecture. Or the SDS Sigma series, for that matter.
[snip]
Rich Alderson
Server Engineer, PDPplanet Project
Vulcan, Inc.
505 5th Avenue S, Suite 900
Seattle, WA 98104
mailto:RichA at vulcan.com
(206) 342-2239
(206) 465-2916 cell
--
Joe Chisolm
Computer Translations, Inc.
Marble Falls, Tx.
830-265-8018