17 Aug
2006
17 Aug
'06
3:46 p.m.
The CoCo 3 is
designed round a custom chip called GIME (Graphics,
Interrupts, Memroy Enhancement). It handles all the video side, the
memory mamangement (remmber the 6809 can only directly address 64K), etc.
Said chip outputs a 9 bit multiplexed address (designed to link to the 9
addres pins on 256K bit DRAMs), and the DRAM timing signals. It also
expects 16 bit wide memory IIRC.
Ah, OK.
It's probably possible to add external
circuitry to turn that back into a
normal 18 bit address and hang SRAM off it, but I think it's more work
than finding some 41256s...
I would assume the controller would exploit page mode references
(especially when dealing with sequential accesses like video). If so, this muddies any attempt to convert
multiplexed
addresses back to a form suitable for SRAM (unless you use
SRAMs that also support page mode access!)
Yes, assuming it produces an 18bit (9R+9C) address, 41256's
It does...
would be the right way to go.
There are 2 standard memory configurations for the CoCo3. The first is a
128K system using 4 off 41464 (64K*4) chips on the mainboard. The second
is a 512K system using a duaghterboard that takes 16 off 41256s. Note
that 256K*4 parts can't easily be used, since IIRC they have 10 address
lines and need a 10-8 split of the 18 address bits.
I am really thinking back now, but there are a couple of RC networks on
the CoCo3 board that fiddle the RAS and CAS timing. I seem to remember
you remvoe at least one of the capacitors when you go from 128K to 512K
(as well as pulling the 4 soccketed DRAMs from the mainboard [1] and
fitting the daughterboard). I did this many years ago, when the CoCo3 was
still in production.
[1] And those 64K*4 chips are just what you need to bring CoCo2's from
16K to 64K. IIRC, that's where the ones from my CoCo3 ended up.
-tony