9 Oct
2018
9 Oct
'18
6:37 p.m.
On Tue, Oct 9, 2018 at 5:14 PM Ethan Dicks via cctalk
<cctalk at classiccmp.org> wrote:
There's little point in wiring 8 of them up into a byte vs using a
62256 except for speed. 55ns is faster than any 8MHz machine really
needs (100ns-150ns was typical for those depending on bus
architecture). I could see these being cache RAM for a minicomputer
vs primary RAM.
Or maybe used as writable microcode control store? Although as x1
parts there would probably need to be a large number of them in
parallel for microcode control store.
For example the HP 1000 A900 12205 control store option from the early
1980s used the same 16K density and 55ns speed INMOS IMS1420 SRAM
chips, but in a 4Kx4 organization, using 12 of them for a 48-bit wide
microcode word. That would take up a lot of board space using x1
parts.