6 Dec
2008
6 Dec
'08
10:37 a.m.
Tony Duell wrote:
That's just... sick. Beautifully sick :-)
Why?
There's an interesting parallel with the design of desktop calculators
(one of my interests, probably on-topic). Some companies built them of
essentially random logic. Others, HP in particular, made a processor, and
added firmware to make it behave as a calcuator. I find the second design
considerably more interesting.
[As an aside, HP made a 16-bit bit serial processor in around 100 TTL
chips including 9 PROMs (7 for microcode, 2 for the ALU, which was
implemented as a loookup table). This was used in the 98x0 family, and is
quite an interesting design).
Tony,
it MAY be possible, but I'm hard pressed to NOT believe in a PS/2
It's certainly possible. After all you can build a processor using only
TTL chip, that was done many, many, times. Rememebr that the 74xxx TTL
family does include some small RAMs and fusible link PROMs :-) So you
could build a processor with data storage (RAM) and program memory
(PROM). And surely you agree the interface is possible using a processor.
Now, for the next challenge, could it be done without the PROM and RAM ICs?
Of course. You cam make anything from 7400s (NAND gates) if you have
anough of them :-)
Gut-feeling is maybe something based around feeding
scan codes into a giant
shift register and comparing that to some hard-wired lookup table on the PCB
(in effect a ROM, just without the IC) might be possible. Clock the relevant
data in parallel out of the 'ROM' and...
A ROM can be considered to be an address decoder (for each combination of
the address inputs, one output of this decoder is asseted), followed by a
matrix of OR gates. The idea is that for each data output you OR together
those address decoder outputs that correspond to addresses that have a
'1' in that position of the word. So you could, in theory, use TTL
decoders ('138, '154, etc) and NAND (those decoders have active-low
outputs) the appropiate outputs of those together to make a ROM.
[An aside again. The address decoder is a matrix of AND gates that AND
different combinatiuons of address inputs and their inverses. So PROM
consists of a fixed AND matrix follwed by a programmable OR matrix. If
you have programmable AND matirx (you get to determine which inputs
and/or their inverses get ANDed toegtehr to make each output of the first
part of the chip) foillwoed by a fixed OR matrix (but the outputs of
those AND gate are ORed together in a way determined by the IC
manufactuer), then you have the classic PAL architecture. Some early PLAs
(82S100, etc) let you progam both matrices, but there weren't enough AND
terms 'in the middle' to let you make evey possible circuit with the
given number of inputs and outputs]
Of course you can make RAM by having D-types to store the bits, an
decoder to decode the address on writing and clock the data into the
appropriate D-types and multipelxers to select a particular word of
D-types for reading. I actually did this once when I needed a high-speed
(I was using F TTL) 8-byte RAM with separate read and write address
inputs.
-tony