8 Feb
2010
8 Feb
'10
11:50 a.m.
Personally I pity those who never get into VHDL and
stay with Verilog,
and I will choose VHDL over Verilog any day.
Agree :-)
Oh the agony when forced to use a Verilog testbench
from our US
collegues.....
Oh, let's do it in SystemC - that cures every pain!
Philipp :-)