1 Oct
2014
1 Oct
'14
2:06 a.m.
On Wed, Oct 1, 2014 at 1:06 AM, Wouter de Waal <wrm at dw.co.za> wrote:
My thinking is that a PAL with 8 registers has at
maximum 256 states.
If it has 8 registers and no additional combinatorial feedback. That's true for
a PAL16R8, IIRC.
Therefore I should be able to apply a vector, clock
the PAL 256 times, and
that would give me all the states.
That doesn't follow logically.
A state diagram of the 256 states will probably have multi-way branches
and mulitple loops, such that there is no 256-step circuit of all 256 states.
If the PAL has some combinatorial feedback, then some state transistions
may occur independent of the pin used to clock the registers.
Even in the absence of combinatorial feedback, there may be states that
are not reachable except on initial power-up or by violation of register
setup time. In a proper design, all illegal states would eventually transition
to legal states, possibly by some combination of inputs specifically
designated for initialization, or simply by careful planning (e.g., the way the
illegal states of a 74160 decade counter all will eventually count to a legal
state, even without the use of the reset input).
To duplicate the PAL properly, even the behavior of illegal states has to
be duplicated, unless you know that there is a reset sequence that will
be used in the target system.
Some programmable logic devices have test mode functionality to force
the registers into a known state. The earliest PALs don't have this as
a documented feature, so they probably don't have it at all.