"stop bits"; was: NEC uPD7201 misfeature

On 01/24/2014 12:06 PM, Eric Smith wrote: It was demonstrated using a pseudo-DPLL running at 16x data rate and lacking edges to sync on it would "center" itself. It only needed one edge to determine early or late and the next edge was enough to correct it if wrong. Since async always has at least one transition (start bit) thats enough to assure the mid bit sample was correctly timed. Generally Async ran at 16, 32, or 64X baud clock and the logic would sample at the numerical halfway mark. Since the source clock and destination clocks were guaranteed (by convention and spec) to be within a fraction of a percent this worked well as you resynchronized every character time during the stop bit "time" A common trick was to send two stop bits and receiver using only one stop bit as this assured one bit time to resync. Further the half way point was a very wide target and the two clocks (TX and RX) would have to be far apart to fail in a character. To fail you have to be more than half a bit time off at the end of 10 bit times or about 2% clock error. Crystals used for clocks then were typically 50 to 100 ppM over temperature range and at room temp less. Async to async was fairly bullet proof for most mediums that didn't exhibit time shift. FYI: the mits ACR used a async and tolerated a fair mismatch in rate but was very intolerent of short term jitter as could be cause by irregular tape speed occurring at a fast (1/15 to 1/30th of a second) rate. Reason is it was FSK without clock recovery or sychronization and drove a simple UART. Allison