23 Jun
2007
23 Jun
'07
10:51 a.m.
On 23 Jun 2007 at 10:30, Al Kossow wrote:
That reminds
me that a very fast cpu chip was designed for very fast
multi-tasking.Poiled I/O is faster than a IRQ could be because you
can change threads very quickly.
Ubicom
http://www.elecdesign.com/Articles/ArticleID/3151/3151.html From the article:
"If an HRT thread is waiting for an interrupt, or if it's not ready,
then its slots can be used by NRT threads. These are scheduled in a
round-robin fashion, with each thread getting one slot every time it
runs."
This would seem to indicate that interrupts are part of the chip--or
that the original author meant to say "event" instead of "interrupt".
The CDC 6000 series used a 10 way multithreaded architecture
virtualized as 10 independent 12-bit processors for I/O. No
interrupts necessary there either. But then, back in 1964, I don't
know if the word "multithreaded" had been invented yet.
Cheers,
Chuck