Ethan Dicks wrote:
On 2/5/10, Chuck Guzis <cclist at sydex.com>
wrote:
Really? I don't think I've seen a single
piece of modern gear made
in the last 10 years that uses an 8255 to interface to an IDE drive.
They do have specialized chips to do that...
If it's the hobbyist clan, well, that's a different matter. I'd
think even a small CPLD would do a better job.
The Spare Time Gizmos SBC6120 happens to use an 8255 for its IDE
interface. It has three GALs and no CPLDs. It is less than 10 years
old.
-ethan
Using an 8255 makes it electrically simple and trades for programming.
However.. it's slower than sludge doing it that way. I have done it that
way (using BCC180 Micromint Z180 card) as it had 8255s on it and its
about 8x-10x slower than doing a real direct port IO.
NOTE: all the IDE interface is is a address decode and bus buffer
as all the intelligence is on the drive. Most System that use IDE
are 80x86 or other 16bit wide(or wider) systems. The reason to
use 8255 on small micros (8051, 8085, z80, z180, 6502 6809) is
that IDE data path is 16bits wide and the using two ports of the
8255 you can do the needed byte latch to transfer 16bits is two
reads or writes. Other designs use TTL or maybe a GAL (GIDE)
to perform that or as I did I just ignore the upper 8bits and treat
the device as 256bytes/sector rather than 512. However the
amount of TTL to do the latch the upper byte bidirectionally
is fairly small for those that wish a purist interface. But with
large hundreds of megabytes to small 10s of gigabytes throwing
every other byte away is a small to no cost. Also later drives
use LBA addressing which is far easier to work with then CHS.
One caveat.. USE CF and that does the 8bit transfer that IDE
documented but only a few old drives implemented. That works
well and require only two address blocks to work and near zero
logic beyond address selection and buffers where needed.
Anywho the IDE interface chips from the PC market are all basically
16bit wide bus, IDE drive 0,1 address decode and some extra logic
to do burst mode DMA, block DMA (Both required external DMA
support) or PIO. in the x86 space. FYI PIO unlike floppies is buffered
on the disk so the IO can be does as fast or slow as the programmer
wishes to the limits of ATAPI spec (all do minimally 33mbytes/sec
and later are faster).
Allison