S-100 IDE project

Hi! 2009/11/7 Andrew Lynch <lynchaj at yahoo.com>: This 8255 schematik is damn slow since requires about 20..30 commands, time delay loops and massive I/O. The resulting speed is about 10..20 K/s There is better schematic floatind around, which use "shadow" 8-bit latch (273/573) for HI and LO bytes to mux/demux 16-bit IDE bus to 8-bit system bus. It uses _system_ R/W, does not require loops and thus much faster. One example (with lot of links): http://www.hanssummers.com/computers/cpcng/ide/index.htm Another example, with ASCII-ART schematic and CP/M BIOS sources (with Russian comments): http://sensi.org/~svo/scalar/media/w/hdd.zip This scematic gives full I/O bus speed divided by 2 for reading but requres some "pointer magic" for writing and writing is a bit slower. (the LO register at 50H, the HI "shadow" register at 58H) ;write sector SAVE: INR L ; select an ADDR+1 i.e. HI byte MOV A,M OUT 58H ; prepare HI byte _before_ IDE bus transaction DCR L ; return to ADDR i.e. LO byte MOV A,M OUT 50H ; write LO byte and initiate IDE bus transaction INR L INR L JNZ SAVE There is also VCI XTIDE project. They seems use similar schematic with 573 lathes but they does not publish schematic and sources http://wiki.vintage-computer.com/index.php?title=XTIDE_project P.S. Buildind IDE controller for 8-bit is a pandemy like a swine flu... ;) -- -=AV=-