Q-bus to CF [was: IOmega]

FYI in the bus transaction sense is what counts as the device in this case the IDE disks sees that. The fix is simple isolate reads and writes. When I say bus I'm talking physical hardware interface not the "software" interface or other hardware abstactions. In the VAX case the Qbus or Ubus behaves the same as PDP11 even if the read is thrown away. Doesnt need smarts. It only has to look like an SL! you have a series of about 8 registers, some read, some write and some are read/write for example the data register. Any incidental reads or writes to the data register during a transfer is unexpected and messes with the IDE (DISK) internal smarts. So the logic has to make that bunch or registers look like distinct read and write addresses that do not overlap. Thats why the serial line interfaces for U and Q buses need 4 addresses, Control write, Data write, Status read and Data read. Right, however it has to be done right or it doesn't work. Bob understands that designed accordingly. The read before write problem is important to status and data registers becuase if you touch them at the wrong time (like an incidental read when you mena to write) the devices internal logic is slightly messed up. The fix and even DEC does things for DL devices (and others) is that the write is gated to one set of addresses and the read is to another. Adds a little logic but nothing complex. Allison