>>>> "Tony" == Tony Duell
<ard(a)p850ug1.demon.co.uk> writes:
> What parts do not have published programming
algorithms? I you are
> buying your
Tony> I have yet to find a reasomably complex PLD (that is
something
Tony> more than one of the ispGALs) that is 100% documented. That is
Tony> to say that you can go from logic equations to chip without any
Tony> proprietary software, either the logic compiler or the
Tony> programming software.
That's a good point though I think the big issue there is the early
steps. The programming itself is often easy since it doesn't use odd
voltages or timings, just a plain bitstream clocked in via a serial
port. One of the FPGA vendors created a particularly clean setup
called "Jaz" (forgot who -- Altera?), I wrote software to drive that
which was quite painless.
But the real issue is that NO ONE will tell you the internals of their
FPGA, so you can't figure out the bit patterns that you need to
perform a given logic function. Too bad really, because the logic
synthesis software available from the chip vendors often sucks pretty
badly. I have a bunch of battle scars coping with really stupid bugs
in Lattice tools, which will not be fixed since they are apparently
considered normal behavior.
I think if you have infinite pull the situation is sometimes better --
I've seen some evidence that DEC was able to get Xilinx to tell it how
to synthesize for those chips. And they did it much better... but
those were research tools in the Palo Alto group only.
paul