15 Aug
2006
15 Aug
'06
5:32 p.m.
From: "C. H. Dickman" <chd_1 at nktelco.net>
Tony Duell wrote:
The signal in
question is ROM ADDRESS L. The MM8-E uses this as an extra
select line, unconditionally deselecting when low. Presumably when the
ROM decodes its address, it pulls this low, disabling all R/W memory. A
neat way to make a hole. The MR8-E section of the maintenance manual
confirms this.
Thanks! (I had eventually figured this first part out :-).)
From:
"Al Kossow" <aek at bitsavers.org>
That one is much clearer,
though I cannot find the logic in it
(if any) that inhibits reads when using the bootstrap cards.
The bootstrap ROM in my 8/e is a diode matrix ROM that doesn't appear in
the memory map. When you flip the 'SW' switch, the boot ROM pretends to
be a front panel and copies itself into the appropriate bit of core. Another effect of ROM ADDRESS L is that it prevents
the PC from being
incremented (to skip over the return address) during the execute state
of a JMS instruction. This is stated in the Small Computer Handbook and
in the KK8-E Processor Flow Chart. The SCH says that this is to save a
ROM location. Wouldn't a JMP instruction be just as effective?
This was news to me. I wonder if the CPU still wastes a cycle trying to
store the return address.
Anyway, this is just the level of information I was looking for. Often
in the schematic I can puzzle out what is being done, but not why. If I
don't know the why, then I can't figure out if whatever they're doing is
relevant to whatever I'm trying to do.
Another example is that the bitsavers document Al referred me to latches
the RAM data (using STROBE), rather than having the RAM continue to
maintain it. I don't know why they did that, so I can't tell if it is
important for me to do it too. (I can get a much lower component count
if I can just "stretch" my SRAM read until the cpu has seen the data.)
Vince