14 Jan
2013
14 Jan
'13
1:49 p.m.
On 14/01/13 2:15 AM, Mouse wrote:
Maybe. Depends on what limits "the DMA transfer rate". In general,
it's possible, depending on the memory subsystem, that DMA out of
memory does not interfere with CPU access to memory unless they are
accessing locations too close to one another (eg, the same 32-bit line
Is that true of Qbus, though? I thought a memory cycle monopolises the bus.
Admittedly it's a few years since I studied Qbus in detail. Maybe I'll
go hit the books again. I still have hope of making bus cycles from an FPGA.
--Toby
[...]; the DMA transfer rate may not be the limiting
factor.
You'd have to halve the rate in any case since the CPU would take an
equal amount of time doing memory cycles to update it? of memory). Also possible is that the memory bus is
enough faster than
both the DMA path and the CPU path that, while they can collide over
it, it can sustain both data streams at once without trouble.
I don't know enough of PDP-11 memory subsystems to know whether either
of those is true of any of them, though.
/~\ The ASCII Mouse
\ / Ribbon Campaign
X Against HTML mouse at rodents-montreal.org
/ \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B