24 Oct
2016
24 Oct
'16
1:35 p.m.
On Oct 24, 2016, at 1:30 PM, Paul Koning
<paulkoning at comcast.net> wrote:
OK, I guess my last email didn?t make it. It appears to me that the rise time is set at
25ns.
You need to look at the PDP-11 UNIBUS Design Description document on Bitsavers. Firstly,
in section 4-1, it specifies which chips to use and recommends not using a whole list of
other
chips. The only recommended chips are: 8640, 8641 and 8881.
There are a number of rules that must be adhered to when building out a Unibus system.
These
include:
Maximum cable length must be < 50?
Maximum DC loading < 20
Maximum lumped loading < 20
There are rules where cable lengths must be *increased* to avoid reflections.
A single Unibus can be divided into multiple segments. Each segment must adhere to the
above
rules, so you can see that a Unibus can be quite large.
For example, my PDP-11/40 resides in 2 BA11-F boxes (23? tall) and are fully populated
with
Unibus backplanes (5 9 slot backplanes each) with a BA11-15 (15? cable) connecting the
two.
My point here is that the Unibus has a very different electrical environment than Q-bus or
Omnibus
and what may work for them will probably have troubles on a Unibus.
TTFN - Guy
On Oct 24, 2016, at 3:55 PM, David Bridgham
<dab at froghouse.org> wrote:
On 10/24/2016 12:01 PM, Paul Koning wrote:
I don't see any max slew rate spec in the driver specs in the peripherals handbook.
I don't know about the receiver part, but
I'd expect that the drivers could very easily be done with a simple transistor
circuit.
Agreed. However ...
As for slew rates, unless you have antique
transistors, that's not going to be an issue given that you meet the current sink
spec; the slew rate of an OC circuit is determined by the system capacitance and the sink
current of the driver.
I think you read this part backwards. The slew rate requirement is not
a minimum slew rate but a maximum one. That is, any modern transistor
(probably ancient ones too) will be way too fast. You have to do
something to slow it down. Still, I think this one is easily met as
it's just a series resistor on the gate of the driver MOSFET working
against the gate capacitance. Some FPGAs have current limiting on their
output which may obviate the need for the resistor even.