12 Jul
2016
12 Jul
'16
6:05 a.m.
Time to dust of the 50 panel hidden in the basement.
-pete
On Tue, Jul 12, 2016 at 1:55 AM, Camiel Vanderhoeven
<iamcamiel at gmail.com> wrote:
Op 12 jul. 2016 10:14 a.m. schreef "Dave
Wade" <dave.g4ugm at gmail.com>:
> -----Original Message-----
> From: cctalk [mailto:cctalk-bounces at classiccmp.org] On Behalf Of Curious
> Marc
> Sent: 12 July 2016 08:58
> To: General Discussion: On-Topic and Off-Topic Posts
> <cctalk at classiccmp.org>
> Subject: Re: IBM 360/30 in verilog
>
> Darn. My hopes are shattered. Lots of Verilog in my future, that is if
we
can
Sure, a generic one would be simpler, but the point of doing an accurate
one of a specific model (65 in my case) is to accurately drive the panel
that shows the internal registers and opening of gates.
find 360/50 ALDs...
Marc
It actually might be easier to produce a generic S/360 clone in FPGA using
the POP rather than individual ALU's.
Having built a very simple CPU (in VHDL not Verilog) and planning to start
on a more complex (Ferranti Pegasus)
Of course it wouldn't be cycle accurate, but perhaps that wouldn't be
important.