8 MHz
crystal clock.
1 62C1024 128K*8 SRAM.
1 Xilinx CPLD (XC9572 should more than handle
it)
The CPLD comes in a PLCC (44 pin) and thus is "hacker friendly" If you send
me a schematic I can generate a bit file for the PLD. Digikey sells these
for $5.53 in single quantities, if we can get by with fewer logic cells
then the cheaper one is $3.30 each in single quantities.
I've actually been thinking about doing something like this. The advantage
of the FPGA is you could program it in situ. If you know the controller that
was really supposed to read the disk, you could probably just emulate that
controller in the gate array. Of course, this is more complexity, but it
is optional complexity. The default configuration would be the sample
everything and sort it all out later version.
Eric