Which Dec Emulation is the MOST useful and Versatile?

True. And by some argument, an FPGA implementation (from an HDL behavioral model) is also a software implementation, just written in a different programming language. Recently I commented to an old colleague that there are many different levels of emulation possible, and any one of those may make sense -- it's just a question of what you're after. So you can emulate in a conventional programming language, as SIMH does, reproducing the programmer-visible behavior of the machine but not its timing. Bugs from the original might appear if those bugs are known to be important, but probably not otherwise. This kind is (nowadays) likely to run faster than the original; certainly it won't usually mimic the original timing, neither for computation nor I/O. You can make timing-accurate software emulators, with lots of work. SIMH, in paced mode, and provided the I/O waits are reasonably accurately expressed in units of machine cycles, isn't quite timing accurate but is somewhat similar. You can build a behavioral simulator (SIMH style, basically) in an FPGA. That isn't necessarily any more capable or accurate than a software simulator. PDP-2011 is an example I know of, and I've see articles about other PDP emulations of this kind. Since the design is new, created from a behavioral description (data book, functional spec, architecture spec) it will be about as accurate as SIMH. You can also, if the data exists, build a lower level (gate level or thereabouts) FPGA model. Given schematics and wire lists, it should be possible to build an implementation that's an exact copy of how the original machine worked (assuming of course the documentation is accurate, which is not necessarily the case). Such an emulation would replicate strange and undocumented behavior of the original -- and allow you to find out where that came from. I've been working on such a thing for the CDC 6600, which is surprisingly hard given that the design lives right on the hairy edge of not working at all timing-wise. But it does accuarately model the peripheral processors right now, and indeed it shows and explains some undocumented oddities that are part of that machine's folklore. So it's a question of what you're after. If you want to run the software, or teach the machine at the programmer level, SIMH or equivalent is quite adequate. If you want to teach FPGA skills, an FPGA behavioral model emulation is a good project, especially for a small machine like a PDP-8. As for the gate level model, I'm not sure what argument to make for that other than "paul is a bit crazy" and "because the data exists to do it". :-) paul