2 Oct
2010
2 Oct
'10
10:28 a.m.
On 02/10/2010 10:50 AM, Eric Smith wrote:
On 10/01/2010 07:16 PM, Chuck Guzis wrote:
Then again watch the hardware, a FPGA with fast hardware ripple carry
may do something sneaky to the logic.
patent 4,298,952 uses
ancillary logic to generate a carry-lookahead signal independent of
the adder. I'm not sure if this accomplishes much.
It does exactly what you've asked for. The point of it is that if you're
using off-the shelf parts, or off-the-shelf standard cells in an ASIC,
you already can get adders with the carry lookahead logic. In an FPGA
you don't, so the dual-adder design you described (and Sun patented)
will generally have lower resource utilization and be faster. Eric
Ben,who is back to designing on paper since I can't find a
ISB jtag cable here in Canada.