TI99: TIcK OS (a little to one side of topic)

< >Another is more complex but offers a few more possibilities. Use on the < >the interrupt levels and put ram at the rom addresses. The load vector < >can then be used to copy the ROMS from somewhere else to low memory. By < >doing this rom patching can be done or complete overlay of that 8k space < < Of course, but it also would require a *lot* of hacking to get done < and has some potential dangers. Mind you, P0 and P1 are free on the < 9901 and could be used as "page bits" for multiple segments of < ROM/RAM. Personally I like to keep things simple. Writing ROM < overlays is not fun and I'd rather avoid it. B'sides, if I can get < away with just using 2 *Very cheap* TTL components, so be it. I'll < still put POLLs in my software, but I'll include an IFD in my macro < and compile 2 versions, one with, one without. Not really. the trick used in 9900s is to use load to start a rom based program that copies itself to where ever needed and then turns itself off. The way I'd do it is to put a small rom at F000h and ram where the old roms were. The old rom can then be located at D000h with only a few bits (one) needed to turn off the old roms and the boot room. I do this all the time with Z80s to get the system totaly ram based but with the advantages of rom start up/restart. The trivial trick is to make it seem invisible. the big advantage is if you want to use the memory for something else you can but makesure to do a relod if you want things back to normal. I recently got an extra console that will be modified so that a pair of 32kx8s will map in to where rom, and 32kb expansion ram would be. IE: 0000->3fffh and A000->FFFFh. using 2 32kx8s keeps the chip count low even though 50% is wasted, besides they are cheap. The effect is the system could be much faster as it does not need the PEB access for base ram. I may want to yuse the full 64kb of the pars so I need to know how one of the larger cards like the corcomp 512k map. Do they do it as if it were multiples of 32k or are the two segments (2000->3FFFh and A000->FFFFh) mapped seperately or is it done in 8k segments? < Just a little FIFO would work well, but then, if the CPU bottlenecks < on data because it is physically too slow to even PROCESS the data, < such high data rates become useless and potentially dangerous. Not really it's a matter of buffering the data and post processing it when the tide slows or issueing an Xoff/suspend to stop the flow before the buffer overfills. This situation is nothing new, though in the world of CPU with clocks in the UHF region people may forget that. However the problems of data arriving faster than it can be processed is old hat. Besides with a ramdisk buffering a few kb of data is nothing. Allison