20 Jun
2012
20 Jun
'12
3:06 p.m.
On Wed, Jun 20, 2012 at 8:18 AM, David Riley <fraveydank at gmail.com> wrote:
Of course, a PAL does
handle the somewhat complex 68000 bus logic, which I guess would be
the real magic behind a 68K board.
In a complex 68000 design, with 1980s-era memories that are slower
than bus speed for, say, a typical 8MHz CPU, or slower peripheral
chips (2MHz max 6821...), yes, the bus logic can be quite involved.
A new design with sub-100ns SRAM and 8MHz-capable peripheral chips
would be quite streamlined by comparison - if you weren't planning on
maxing out memory space for RAM and could just use A22-A23 to carve
out large swaths of address space for RAM, ROM, and I/O which would
avoid complex address decoding logic. It's a little more elaborate if
you want to have, say, 14MB of RAM space, 1MB of ROM space, and 1MB of
I/O space - that's when most designs turn to address-select PALs.
-ethan