6 May
2007
6 May
'07
7:58 p.m.
On 6 May 2007 at 15:39, Patrick Finnegan wrote:
Right, and I was trying to point out, that
FPGA-implemented CPU
architecture isn't anything like the variety of commonly availble CPU
architectures that there were in the 60's/70's and earlier. Back then,
every manufacturer (pretty much) had their own architectures, and
"commonly" availble machines might have 8, 12, 16, 32, 36, 60-bit, etc
CPUs, or use 1's complement arithmatic (or magnitude and sign), instead
of 2's complement. (Or, a non-base-2 numbering scheme such as BCD,
2-4-2-1, hollerith code, etc.)
Anent that, in EETimes about a week ago, Clive Maxfield wrote about a
movement to implement decimal floating point for the financial folks--
implemented in FPGA as a coprocessor.
http://www.pldesignline.com/showArticle.jhtml;jsessionid=KACYJ2NGXHOEI
QSNDLRCKHSCJUNN2JVN?articleID=199001229
I'm not certain if the representation is BCD or DPD, however.
Cheers,
Chuck