17 Jan
2014
17 Jan
'14
4:03 a.m.
I wonder what would happen if someone dropped a
68010 into a Canon Cat.
Was that the only move instruction?
Dwight
----------------------------------------
Date: Thu, 16 Jan 2014 18:01:29 -0800
From: cclist at sydex.com
To:
Subject: Re: Motorola 68008 (was Re: Retrospective on the Sinclair QL, 30 years later)
On 01/16/2014 04:52 PM, Eric Smith wrote:
The MC68010 (and 012, 020, and 030) use
instruction continuation, not
instruction restart. On a bus error or address error they write nearly the
entire non-architectural state of the processor into a rather large
exception frame on the stack. Most of that frame (sometimes known as the
stack puke) was undocumented. The fields that were documented were the ones
necessary to identify the faulted access, and optionally to complete the
access in the handler. On RTE, the processor would reload its state from
the frame, and unless the handler marked the access as completed jn the
frame, rerun the faulted memory access.
I remember talking with a Moto fellow at some early 80s Wescon, that the
business of virtual memory and the then-very-new 68000 was getting to be
one of the most often-asked questions by engineers wanting to put the
chip with a real supervisor mode and a bus error trap--and having to
tell them that, no, you couldn't do it. (Although there *were*
workarounds--you could run two 68Ks, out-of-phase with one another,
using one to "test the water" a bit ahead of the other--or you could
restrict the instructions used by programs. Neither was really
satisfactory, but there were products using them).
I remember feeling the excitement--and the disappointment. I still have
my freebie manual from Wescon. Still, it was a nice CPU and we did
work up a wirewrap test version that seemed to run well.
--Chuck