28 Jul
2010
28 Jul
'10
7:48 a.m.
Chuck Guzis wrote:
On 27 Jul 2010 at 16:25, Ben wrote:
A very simple 18 bit cpu, I have fit in 128 cell CPLD.
I have the CPLD logic defined but I still need to revise my
Glue CPLD's, before I start working on PCB.
Two glue 64 cell CPLD's, 2 EEPROMS, 2 32Kbx8 ram, 6850
and the 128 CPLD will comprise the system.A IDE interface
is planned, but I have finished the resolving the I/O yet.
A .8 us memory cycle is planned, with 1.6 us needed for
a 18 bit memory access. Consider it a stretched PDP8
with ISZ,JSR, and I/O instructions missing.
The PDP 8 style code was ment to be:
TAD (.+1)
JMP SUB
Or some machines like the one I am working on;
one does not even have
a CALL of any kind. It is not needed. TAD I [.+1 JMP SUB
It *looks* like PDP-8 code, but that can't be as the PDP-8 has a JMS
instruction. What machine is this? --Chuck
Ben.