1 Mar
2015
1 Mar
'15
1:56 p.m.
On 2015-03-01 22:39, Jon Elson wrote:
On 03/01/2015 11:59 AM, Al Kossow wrote:
I don't think so. On the PDP-8 at least, the increment of the PC is done
at different clock phases for different reasons, and they are not
combined. I/O peripherals can also increment the PC, and it happens at a
defined time.
The clock state machine of the PDP-8 is somewhat complex compared to
more "modern" machines.
Johnny
--
Johnny Billquist || "I'm on a bus
|| on a psychedelic trip
email: bqt at softjar.se || Reading murder books
pdp is alive! || tryin' to stay hip" - B. Idol
On 3/1/15 3:42 AM, Johnny Billquist wrote:
Oh, I KNOW why they did it, it was a VERY simple operation to wire up
in the control logic of the CPU. But, I really like the instruction
layout of
the PDP-11, which was a VERY different paradigm, entirely!
On the PDP-5/8 and the -7, I am guessing they DON'T incr the PC an
extra time, they set up for increment through the main adder, and then
make a carry-in if they want to double-increment the PC. The SKIP paradigm isn't so bad, in my mind.
It makes sense on machines with a single word order code. Incr
instruction
pointer by one and you're done. It makes much less sense on multi-word
order
codes where you have to crack the instruction to see how far to
advance the
instruction pointer.