10 Jul
2005
10 Jul
'05
1:51 p.m.
On Fri, 2005-07-08 at 23:51 +0100, Tony Duell wrote:
Yep, that's certainly what it looks like anyway...
Having had a better read of the timing diagrams, that looks to be the
case. The critical one is the time between the target asserting REQ and
the controller asserting ACK - but in all 'simple' SASI/SCSI interfaces
that bit's done in hardware via a flipflop, so time taken for the
software-driven part doesn't actually matter.
Time to throw a few chips together and have a play around I think...
cheers
Jules
Actually,
I'd not heard of the blue-cased machines before. Maybe they're
in standard off-the-shelf instrument cases rather than with RML logos,
panel cut-outs etc.?
The black case is a standard (Vero iIRC) case. It was designed to take a
19" rack chassis, but RML just mounted the PSU and card guides inside.
OK, the cutouts and logos are custom, but that's all. Oh, Xebec
board in my fileserver is an S1410, for which I have a manual
and a couple of spare boards, so I can do some messing around with a PC
parallel port driver. There's even a sample Z80 interface schematic in
the back of the manual that's probably adaptable...
Still concerned about timings though as some of the timing diagrams do
have upper constraints on signal changes (a lot of them only specify a
minimum limit). Time will tell if the PC's port is quick enough...
I think (wihtout trying it), you can go as slowly as you like.