FPGAs and PDP-11's

Well, the 650x is a VERY thrifty architecture. It has no memory-to memory operations, nor does it have any operations involving more than one register at a time.

[... about resources]

I've taken a good hard look at implementing the 6500 core in XILINX and find that performance, which is VERY much of interest, is impacted most by ALU design. Now, the Virtex CLB allows a single CLB to function as a two-bit full-adder. If one wants the best performance/resource allocation tradeoff, I'm nearly convinced that the best way might be to design it with a 2-bit ALU slice because the resource consumption is small yet the delay for a 2-bit registered implementation of an 8-bit ALU would be just as fast as an 8-bit implementation because of the carry delay from stage to stage. It appears to me that the rate-determining step, then, becomes how fast a clock can be routed through the array. In the case of the 2-bit slice, it doesn't have to propagate very far to get the job done.

With an 8-bit implementation, there's a lot more routing delay, and at least four times as much delay per cycle in order to allow the carry to settle. Since the ALU is used more than once per machine cycle . . . (see where all this leads?)