15 Feb
2021
15 Feb
'21
12:13 p.m.
On 2/15/21 11:51 AM, Fred Cisin via cctalk wrote:
(This is from memory (error prone?).? The WD1791
datasheet should have
more detail, including CRC algorithm?, the specific requirements for the
address marks, and gap contents (write splice, synchronization, etc.))
The thing to note is that the mark (data or address) is almost always
included in the CRC calculation.
Also, some early representations could have non-powers of 2 sector
lengths. (the WD1781 for example, encoded the length in multiples of 16
bytes; the Zilog MCZ used 132 byte sectors). But they are the exceptions.
--Chuck