On Jul 21, 2016, at 4:22 PM, Peter Corlett <abuse
at cabal.org.uk> wrote:
On Wed, Jul 20, 2016 at 09:02:41PM +0200, Liam Proven wrote:
On 19 July 2016 at 17:04, Peter Corlett <abuse
at cabal.org.uk> wrote:
[...]
RISC
implies a load-store architecture, so that claim is redundant.
Could you expand on
that, please? I think that IKWYM but I'm not sure.
A load-store architecture is one where the ALU only operates on registers. The
name comes from having separate instructions to load registers from memory, and
store them to memory.
The converse is register-memory, where ALU instructions can work directly on
memory. However, this means that the instructions have to do quite a lot of
work because now data has to be brought in from memory to an anonymous register
to be worked on and then stored back to the same location. This also results in
a proliferation of instruction and addressing mode combinations. Sounds rather
CISCy, doesn't it?
Meanwhile, a load-store architecture would have to decompose that into simpler
independent load, operate, store instructions. Hey presto, RISC!
I would point out that RISC is not a goal in itself. Instead, the reason RISC is
interesting is that -- at least at some point in the evolution of technology -- it was an
architecture approach that results in more cost effective computers. That is, faster for
the same money or less expensive for a given speed.
It's easy to be led to the equivalence "register-memory instructions" ==
"complex instructions". If you're most familiar with Intel x86, or even
saner architectures like VAX (which have memory to memory instructions, with a pile of
addressing modes), that seems plausible. But, for example, the PDP-8 has register-memory
instructions but it has a very simple instruction set and can be implemented in a tiny
amount of logic. Similarly, register-memory instruction sets were used in many older
architectures, and clearly were easy to do -- if your logic is tubes, you're not
likely to implement large execution units! Even machines like the CDC 6000 peripheral
processors, which have a pile of extra logic for controlling the CPU and surprising
features like a barrel shifter, take only a few thousand gates.
paul