19 Dec
2005
19 Dec
'05
11:07 a.m.
just a note... CPLDs are easier because the EEPROM config is inside the chip (no external
hardware and an easy to use interface). The cost of this is available logic density
though. You will always get more FGA logic space available then you will with a CPLD. Of
course, you can always add more CPLDs, but one FPGA and a 8 pin dip eeprom is less PCB
real estate.
best regards, Steve Thatcher
-----Original Message-----
From: woodelf <bfranchuk at jetnet.ab.ca>
Sent: Dec 19, 2005 2:26 AM
To: General Discussion at null, On-Topic and Off-Topic Posts <cctalk at
classiccmp.org>, null at null
Subject: Re: repairing early HP calcs
Chris M wrote:
I dont own any. But according to a recent Circuit
Cellar article, early ics can be easy to implement in
a FPGA. Dont have the issue in front of me, but the
guy needed to mimic if you will a crt controller.
Therefore could the chips used in the early HPs (maybe
up to and including the 41 series?) be readily
emulated by an FPGA?
CPLD's are a better part as most FPGA's require pre-load from rom.
Still you need the original hardware and docs to create a FPGA design.
Some designers played often some nasty tricks with hardware.
I think for example in the TRS 80 /I a 7400 with a defective unused
gate was used because it was cheaper than a working 7400.