I'd also really like to know why the DMA
controller has two separate
direction control bits -- DMAR/W- and IDMAR/W-... this seems downright
silly, though in keeping with the rest of the TechRef. My "annotated
edition" corrects about a dozen minor and major errors in the register
set descriptions, and adds a bunch of informational sticky-notes and
scribbly comments to reinforce certain points. Ewwww...
I know nothing about this machine, but I seem to rememebr that the
scheamtics on bitsavers contain things that appear to be the schematics
of the DMA and video ASICs in terms of TTL parts. If I am right, that may
be a start in understanding what they actually do.
-tony