Symbolics

On Tue, 29 Feb 2000, Shawn T. Rutledge wrote: On a tagged architecture, instruction data includes 'tag' bits which are used to type the data, and allow runtime data checking in hardware. SPARC processors use a tagged architecture. The processor is stack-based and doesn't have any general purpose registers. I'm assuming this is what makes the hardware stack management more important. The "multiple caches" goes beyond the instruction and data caches common today. "Major caches are the Stack cache, the Memory Map cache, and the Instruction cache." Of these, the memory map cache is the one I find unique; it's an 8K (sic) RAM which "cross references the virtual page number and the physical page number". The instruction cache is part of an optional "Enhanced Performance" unit which I don't have, and also seems to be where the pipeline (three-stage) is implemented. ok r.