RT-11 idle light pattern

(Not RT-11, PDP-11, or even DEC...) The Multics process scheduler quantum is 1/4 second; running processes are interrupted and rescheduled every 1/4 second. The idle process updates the light pattern and sleeps until the 1/4 timer runs out or an interrupt occurs. " " Idle with a flashing pattern in the lights. " " This is a convenient place to recompute tc_data$max_timer_register, " which is the product of the number of CPUs and the tuning parameter " tc_data$pre_empt_sample time. Either of these values may have " changed due to reconfiguration or tuning parameter changes, and " we don't have much else to do here, so ... ldaq flash_pattern inhibit off <-><-><-><-><-><-><-><-><-><-><-><-> idle_dis: dis 0 inhibit on <+><+><+><+><+><+><+><+><+><+><+><+> " The following code checks to see if a connect has been delayed. " This is done by seeing if the ring alarm register is nonzero. " If it is, the connect must be reissued now. sznc pds$alarm_ring is ring alarm set? tze *+2 if not, skip connect reissue cioc scs$cow_ptrs,1* staq prds$idle_temp save flash pattern ldq tc_data$pre_empt_sample_time mpy tc_data$ncpu tze reload_flash bogus for some reason staq tc_data$max_timer_register reload_flash: ldaq prds$idle_temp alr 35 qlr 1 eax7 0,au flash pattern in X7 lxl4 tc_data$n_eligible # of eligible processes in X4 ldx5 bp|apte.term_processid idle type in X5 lxl6 tc_data$stat+2 # of ready processes in X6 tra idle_dis inhibit off <-><-><-><-><-><-><-><-><-><-><-><-> At the top, the initial pattern is loaded into the A and Q registers; the 'dis' is 'delay until interrupt set': idle the CPU until the count timer expires or interrupt. A few lines later, the A and Q registers are saved in prds$idle_temp. At reload_flash, the pattern is restored from prds$idle_temp into A and Q; the 'alr 35' (A Left Rotate) does a circular rotate of the A register; being 36 bits, this is equivalent to rotating it one bit to the right. The 'qlr 1' (Q Left Rotate) rotates the Q resister to the left one bit. The 'eax7 0,au' (Effective Address to X7) effectively copies the high 18 bits of A into the X7 register; as far as I can tell, this and the next few instructions are strictly diagnostic; the contents of those registers can be displayed on the maintenance panel, but unless the machine was idle, they would quickly be overwritten. Then the code branches back up to the sleep instruction. When the system is idle, the A and Q registers will hold each pattern for a 1/4 second. The initial pattern is: flash_pattern: zero -1,0 zero 0,-1 Which is 6180 assembler weirdness for putting 0777777000000 in A and 0000000777777 into Q. The rotate instructions will make the 18 one bits in the A register circulate to the right; to the left in the Q register. On the maintenance panel, the registers are displayed stacked, A above Q; because of the relative layout of the bits, this produces the illusion that the bits are rotating out of the right end of A into the left end of Q, and similarly of the other end, so the bits are traveling in a circle. The pattern can be seen starting at 1:44 in https://www.youtube.com/watch?v=jni7wk7bjxA -- Charles