6 Sep
2010
6 Sep
'10
12:55 p.m.
On 6 Sep 2010 at 19:46, Philip Pemberton wrote:
On 06/09/10 18:25, Chuck Guzis wrote:
If it's got a "capture" mode on a timer, then jitter and latency are
of little concern--the CPU need only come around often enough to read
the capture register and stash it away. Some DSPs even include a DMA
mode for capture events, so the CPU is more or less out of the loop.
What kind of hard drive MFM resolution are you going for on the DF?
The CW samples floppies at 56MHz; similar resolution on an ordinary
ST506 hard drive would seem to require a clock of 560MHz, which is
high, even for an FPGA.
Synthesizing a commodity floppy controller is of little interest to
me, as much of what I deal with is very far from "standard" 3740-type
floppies. Group code, weird address marks, hard sectoring, unique
CRCs (or even integer checksums) are more the rule. Besides, I think
that the SMSC floppy controller is still available (in TQFP).
--Chuck
Much of what Jens does could now be handled with
most modern medium-
scale microcontrollers. I think that's what most of the other
products, such as the Deviceside do. All you need is a PWM-style
timer with a "capture" mode and the ability to address about 128K of
DRAM and a uC that runs at a sufficient speed to reduce aliasing
effects. There's really no magic involved at all.
Indeed -- the SPS guys are doing one (Kryoflux, google it) with an
Atmel SAM chip (if memory serves). Basically an ARM, Flash ROM and
SRAM on a single chip.
I'd be a little concerned about interrupt latency and jitter (the ARM
is a pipelined RISC design, interrupt timing tends not to be 100%
deterministic) but it's a really cool way to do it cheaply...