29 May
2014
29 May
'14
11:36 a.m.
I remember discussing Honeywell L66 and later performance with an
ex-Honeywell guy, who I think was called Vince Martin, and lived in
Scottsdale , Arizona. He ran a performance tuning consultancy...
He had some code that worked out how many MIPS the machine could
actually do an any point in time. He said that as the I/O had priority
on the memory access, and there wasn't enough memory bandwidth for
everything to work flat out, the available MIPS could vary between "0"
and the rated MIPS of the machine, depending on load. Whats more the
system monitor display (I can't remember what it was called) measured
CPU Busy not MIPS so the system could show 100% CPU Busy and yet be
doing no MIPS what so ever.
He said, but we never tried it, that if you wrote a looping tape i/o you
could kill the entire machine dead as the 6250 BPI drives we had could
totally max the memory bandwidth leaving no way for the CPU to read data....
So an I/O based "halt and catch fire" perhaps...
Dave
G4UGM
On 29/05/2014 19:15, Rich Alderson wrote:
From: Henk
Sent: Thursday, May 29, 2014 1:13 AM
--
Dave Wade G4UGM
Illegitimi Non Carborundum
-----Oorspronkelijk bericht-----
From: Chuck Guzis
Sent: Wednesday, May 28, 2014 10:42 PM
On the other hand, the PDP-10 architecture explicitly allows an XCT as the
argument of an XCT, so the looping scenario is possible. However, the
interrupt system should allow the system to break out on a time-slice
expiration, so only the individual process should hang.
Rich
Rich Alderson
Sr. Systems Engineer
Living Computer Museum
2245 1st Avenue S
Seattle, WA 98134
mailto:RichA at LivingComputerMuseum.org
http://www.LivingComputerMuseum.org/
On 05/28/2014 12:50 PM, Henk wrote:
I remember the EX (execute remote) instruction. I wonder what would
happen if you EX to another EX instruction that EX'd the first EX. That
would cause a loop, I guess. But both systems that I worked on, the
system would not hang, just the CPU executing the EX code.
I seem to recall that
the S/360 had a special exception code for an EX
instruction being the object of another EX instruction.
I have no access to SPERRY documentation, but I would expect
that the 1100 also would recognize EX targeting an other EX and
generate an exception or trap. IIRC the word is 'contingency' in the
1100 jargon for 'exception'. End 80's memory cells starts to fail ...