On Jun 6, 2018, at 3:19 PM, Toby Thain <toby at
telegraphics.com.au> wrote:
On 2018-06-06 2:08 PM, Paul Koning via cctalk wrote:
...
The block diagram manual shows the waveforms generated by the controller. As you can
see, they are pretty angular and straight lined. Each segment (between the small marks on
the stroke) corresponds to a 100 ms clock cycle, with a one or two element step in X
and/or Y.
That must be closer to 100 ns? Typo?
Oops, yes of course, 100 ns (the 6000 series "minor cycle time", the master
clock period).
...
I have converted the "chassis tabs 12" wire lists to a VHDL model, which you
can find on my Subversion server. Run on GHDL, it demonstrates the behavior of the
circuit and reproduces the documented waveforms.
I have also attempted to create a SPICE model of the DD60 deflection signal path. So far
that hasn't been all that successful. I probably have bad assumptions for the
transistor models, and the CRT deflection plate capacitance figures are also a complete
guess. My hope was to reproduce the actual screen patterns, but that hasn't worked
yet.
Finally, I did a much more primitive approximation of the DD60 signal path, with a couple
of IIR filters that very roughly imitate the RC elements in that path. That was done as
part of my console display emulator program for Tom Hunter's DtCyber program. It was
somewhat successful in that the characters show some of the rounding and distortion that
the real display has, but unfortunately I can't claim that this is because it's an
accurate model.
Nice work!
Thanks. If anyone is interested, the bits are open for inspection at
svn://akdesign.dyndns.org/dtcyber/trunk -- the VHDL is in the "vhdl"
subdirectory and the attempt at a SPICE model in the "spice" subdirectory. The
console emulation is dd60.cpp.
paul