Subject: Re: Tarbell is making me insane
From: Grant Stockly <grant at stockly.com>
Date: Wed, 07 Nov 2007 12:07:22 -0900
To: "General Discussion: On-Topic Posts Only" <cctech at
classiccmp.org>,
Pete <petechapman at frontiernet.net>
Welcome to S100.
I don't have info on tarbel 1011 seris FDC. The schematic on hand I
could comment more. However 8" DD with 2mhz 8080 is very difficult
to do as single density is already pushing the 8080 through some very
tight software loops.
I think the crystal on the tarbell has been changed from 4MHz to
2MHz. I do know that one of the failure modes is for the Tarbell to
"crash" within a wait state.
Changing the crystal would half the data rates making it right for
5.25" floppy.
One of the modes all the contrllers that use hang mode (wait), is
sector never found. Wrong clock rate will insure that.
I read the manual and when it started talking about not
using
"Active" wait state generation I was given a hint.
The tarbell as I received it was using XRDY for wait states. My
front panel uses XRDY.
When I was developing the Altair kit I found that the 1k memory card
would NOT deposit or examine because the PRDY was being driven by the
front panel. The 1k memory card would have to basically over power
the front panel buffer. This would cause some nice transients too.
So this morning I changed the tarbell from XRDY to PRDY and it
worked. It has worked fine every time I have tried it since, so
maybe I found the 'BUG'.
It's always Prdy. The 1K card uses it becuse the rams installed were
Sllooowwww and wait states were needed. I'd not use that card ever.
When using A FDC that asserts wait for syncronization you really
don't want memory that insert wait states as the CPU is alreay slow
enough and slow memory is a bad thing.
So, WHY do all these old cards use 8T97 type drivers to
force the
wait line? I guess its only the MITS display board and 1k memory
board that drive the wait line regardless of if they are addressed or
not. Whats wrong with these guys using open collector parts with a pullup???
Both work. The logic however uses the 8T97 and tristates it when
not needed (board not addressed) which is a "legal" way to do it
though it seems like more effort.
Of course using high is active and mixing than with low is active was
a dumb thing too. Even Tristate asserts a better low than a high.
I'll report on how robust it is later on. I've
had several false
starts with this setup...
Also sounds like oneshot problems. Check cpu
timing. Even small timing
errors tend to magnify bus noise issues and incompability problems.
I checked that.
Good, keep checking it as those oneshots are not reliable in my book.
Allison
Grant