24 Oct
2018
24 Oct
'18
6:01 a.m.
From: Paul Koning
A lot more comes from the CPU architecture. The
instruction set, of
course (arguably the first RISC).
An observation about RISC: I've opined before that the CISC->RISC transition
was driven, in part, by the changing balance of CPU speed versus memory
speed: with slow memory and fast CPUs, it makes sense to get as much
execution bang out of every fetch buck (so complex instructions); but when
memory bandwidth goes up, one needs a fast CPU to use it all (so simple
instructions).
It occurs to be that the same balance probably applies to memory _size_. When
memories are small, one wants dense code (which probably means CISC); only
with larger memories does RISC, with its less-dense code, make sense.
Noel