1 Jan
2018
1 Jan
'18
12:56 p.m.
On Mon, Jan 1, 2018 at 12:33 PM, Noel Chiappa via cctalk <
cctalk at classiccmp.org> wrote:
Other CPUs of that era might be the same. There's an amusing description
of the Multics CPU here:
http://www.multicians.org/mga.html#6180
"The 6180 processor was among the last of the great non-microcoded engines.
Entirely asynchronous, its hundred-odd boards would send out requests,
earmark the results for somebody else, swipe somebody else's signals or
data,
and backstab each other in all sorts of amusing ways which occasionally
failed (the 'op not complete' timer would go off and cause a fault). Unlike
the PDP-10, there was no hint of an organized synchronization strategy:
various 'it's ready now', 'ok, go', 'take a cycle' pulses
merely surged
through the vast backpanel ANDed with appropriate state and goosed the next
guy down."
I have the understanding that the design was large blocks of synchronous
logic connected asynchronously. The Control Unit (instruction fetch and
decode), Operations Unit (integer operations), Decimal Unit (decimal and
floating point), Extended Instruction Set (string and bit operations) and
Append Unit (virtrual memory) were all internally synchronous units. The
asynchronous interconnects is supposedly why the GE-635 was the machine
that was made into the GE-645/6180 for Multics: adding the Append Unit was
relatively easy: it was just wedged in between the Operations Unit and the
SCU (memory); the fact that memory access was now slower due to page table
lookup is not an issue as it didn't interfere with bus timing; the CPU just
waited longer for the data.
-- Charles