[personal] Re: PDP-8 on FPGA project & where is Hans Pufal?

A clocked JK with the JK held high will perform the same function.

----- Original Message ----- From: "Tony Duell" <ard at p850ug1.demon.co.uk> To: <cctalk at classiccmp.org> Sent: Saturday, December 20, 2008 6:10 PM Subject: [personal] Re: PDP-8 on FPGA project & where is Hans Pufal? >> > Your code above does not result in latches. It results in D type >> > flipflops! >> >> What's the difference? As I've learned to use the words, D-flops _are_ >> latches. Have I mislearnt? > > As I understand the terms, a D-type flip-flop is edge-triggered, a latch > (or more exactly a transparent latch) is level-operated. > > What I eman is that for a D-type flip-flop, the output (Q) is set equal > to the input (D) a short time after the rising edge (say), of the clock > signal. At all othter times Q does not change state, no matter what D > does. So if clock is held high all the time, or held low all the time, Q > will never change. > > But with a transparent latch, then if the clock (sometimes called the > enable input) is in one sate (say high). then the output (Q) tracks the > input (D). When the clock input goes low, then Q is held in whatever > state it was in as the clock input went low. > > A simple example of the differnce. If you take a D-type flip-flop and > connect the output to a NOT gate and the output of that back to the D > input, then you get a divide-by-2-circuit. Feed in a regular clock at one > frequency and the Q output will toggle at half that frequency. But if you > do the same thing with a transparent latch, you get something that > oscillates at a frequency determined by the propagation delays when the > clock is high. In other words the output is somewhat unpredicatable, it's > certainly not a square wave at half the frequency of the clock signal. > > -tony