1 Jul
2014
1 Jul
'14
6:22 p.m.
On 7/1/2014 1:32 AM, Brent Hilpert wrote:
On 2014 Jun 30, at 8:34 PM, Jim Brain wrote:
The datasheets (at least those found at
http://www.commodore.ca/commodore-manuals/mos-commodore-semiconductor-group…)
are rather poorly specced, they don't go into just what the special
characteristics or input structure of that reset pin are - how the
+10V is sensed internally.
I know, but that's all we have...
Normally, you don't want to drive chip inputs at > Vcc because input
protection diodes or parasitic on-chip diode junctions kick into
forward conduction, drawing current from the chip Vcc, out the input,
through (your PNP transistor), to +10. That clamps the voltage on the
input at Vcc + (~ 0.6 or something greater), in the vicinity of the
+6V you mention.
This reset input is supposedly (the datasheet is contradictory) able
to tolerate excess voltage, but it may need current limiting.
Well, I didn't
have the CPU in the circuit at that point (I wanted it
right before I subjected the CPU). It turns out that I had the bias
wrong on the PNPs and NPN. I upped the current from the IO pin to the
NPN B via a 1K, and tied the E to ground through a 5K. I can now see
perfectly stable 10V and 5V voltages at the RESET pin.
You could/should also add a (say) 1K R from PNP-C to +5 to give a
decent pull-up when both your reset drive transistors are off. (In
proper operation), that should speed up transitions to 'high'/+5 on
the reset input.
I used 10K, which did as you suggest.
Sadly, my test code is not doing anything, so we must not have enough
understanding of the internals. The internal clock is 1/2 external, and
I am running the CPU at 250kHz to ensure enough time for the uC to do
things.
But, thanks for the suggestions. I thought for sure I was losing it...
Jim
--
Jim Brain
brain at jbrain.com
www.jbrain.com