10 May
2010
10 May
'10
8:09 p.m.
On Monday 10 May 2010, Dave McGuire wrote:
On 5/10/10 7:36 PM, Eric Smith wrote:
Running HPL on a modern x86 processor tends to disagree with you (though
on the recent 6+ core chips, memory wait can be significant if you're
pushing all the cores). More likely, it's wasting lots of cycles waiting
on a user or I/O device to do something.
Besides, with the large caches on modern x86 chips, and the codes
"compression" you get by using a CISC architecture instead of those
nasty RISC architectures (though POWER does a good job of this with its
compression), you spend a lot less time waiting on memory. As well, code
fits in the cache better, because it's smaller than what you'd get on a
RISC chip.
Pat
--
Purdue University Research Computing --- http://www.rcac.purdue.edu/
The Computer Refuge --- http://computer-refuge.org
On 05/10/2010 11:43 AM, Tony Duell wrote:
Sometimes! Also, don't forget that most (all?) x86 processors
spend the majority of their wall-clock time waiting for memory. So I ask again. What clock signal is this 2GHz
refering to?
The x86 processors from Intel and AMD contain an internal PLL which
multiplies the external clock to produce an internal clock for the
processor pipeline. Most of the CPU core is running on that core
clock. (In the case of the Pentium 4 and derived processors, some
of it actually operates at twice the core clock.) Instructions take
a variable number of cycles to execute, but there are multiple
instructions "in flight" at any given time. The average number of
instructions executed per clock cycle is greater than one.