5 Mar
2020
5 Mar
'20
6:11 p.m.
On 3/3/2020 8:39 AM, osi.superboard via cctalk wrote:
My assumption is, that the LDA address access is too
late at the end
of the instruction cycle, and the CPU already started the next
instruction cycle internally. HALT will be acknowledged only during
the instruction cycle following the LDA.
It would be interesting to measure, when the LDA pulls down the HALT
compared to the last instruction cycle signal (LIC). Maybe using LDD
will work better, because the HALT signal will be asserted one clock
before the instruction cycle ends.
Which is exactly what I ended up doing:
http://www.go4retro.com/2020/03/05/coco-dma-fighting-on-the-bus/
Jim