11 Jun
2010
11 Jun
'10
2:12 p.m.
On 11 Jun 2010 at 12:11, Eric Smith wrote:
Note that the only data separator worth a damn in the
WDC app note are
the two that use PLLs. The most commonly used was the one in Figure
14 that uses a 74LS629 VCO and the phase comparator of the WD1691.
The circuit by MPI in Figure 13 that uses an MC4024 VCO looks OK but I
haven't seen it used. The rest are crap.
Figure 11 uses a one-shot, and won't work reliably even for single
density. It's comparable to the worthless data separator built into
the 1771. Figure 12 uses a state machine and works approximately the
same way the Apple II read state machine works. It's probably good
enough for single density, but won't work reliably for double density.
There seems to have been a general move toward "good enough" in the
early 80s. The first version of the IBM 5150 floppy controller used
an IBM hybrid-packaged design; the second version used conventional
TTL and a 4024 VCO that was good enough, but not as good as the first
version. I think later controllers (as used in the 5170) used the
all-digital WD9216 type of data seaparator. With the all-in-one FDCs
(WD37C65, N82077), the question of data separator design became a
nonstarter. Just plug it in with no adjustments needed.
I suppose "good enough" accurately describes the Apple II scheme;
"gutless wonder" would be another term that comes to mind. GCR with
the only error conrol being a one-byte arithmetic checksum on each
sector. Were there ever any "turbo" mods to run an Apple II at more
than 2MHz without breaking the floppy logic?
--Chuck